Memory bandwidth reduction for video decoders based on data arrangements

The off-chip memory bandwidth is often a critical part of a video processing system. Traditional cache usually behaves poor since some video algorithms, such as motion compensation, tend to access memory in an inefficient way. An efficient memory bandwidth architecture for video decoder is proposed in this paper. Two bandwidth optimization strategies are proposed through pixels reconstructed and data arrangements without any degradation of picture quality. The experimental results show that two strategies succeed in reducing external memory bandwidth of motion compensation by 30% and the data arrangements strategy can solve the latency problem better than the previous solutions. The proposed algorithm is also computationally simple, reducing latency time and creating sufficient accessibility.