Title :
Modeling of Retention Time for High-Speed Embedded Dynamic Random Access Memories
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
Embedded dynamic random access memory (eDRAM) is becoming a popular choice for large cache applications due to its density, speed, and power benefits. One of the crucial challenges in eDRAM design is meeting the retention time specification. Due to implementation in logic process, usually eDRAM suffers from poor retention time compared to commodity DRAM. The retention time of eDRAM designed in scaled technologies not only depends on bitcell leakage but also on effects such as reference voltage variations, frequency-dependent writeback voltage, and various pattern-dependent coupling noise. Under the strict frequency and power budgets, these second-order mechanisms start playing a major role in determining the array retention time. Designing eDRAM array for certain retention time requires detailed modeling and understanding of the noise sources and variations. This paper investigates these components and provides a model of eDRAM retention time. Our results in 22 nm predictive technology shows that retention time can be impacted by as much as 10-16 × if the noise and variations are not contained in the design.
Keywords :
DRAM chips; cache storage; embedded systems; high-speed integrated circuits; integrated circuit design; integrated circuit modelling; integrated circuit noise; array retention time; bitcell leakage; commodity DRAM; density benefits; eDRAM array design; frequency-dependent writeback voltage; high-speed embedded dynamic random access memory; large cache applications; logic process; noise sources; noise variations; pattern-dependent coupling noise; power benefits; power budgets; predictive technology; reference voltage variations effects; retention time modeling; scaled technology; second-order mechanisms; size 22 nm; speed benefits; strict frequency; Capacitance; Couplings; Logic gates; Noise; Random access memory; Timing; Transistors; Embedded dynamic random access memories (eDRAM); low-power memory; retention modeling;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2014.2312481