Reduction of window layer optical losses in CdS/CdTe solar cells using a float-line manufacturable HRT layer

Buffer, or high-resistance transparent (HRT) layers have been shown to increase the efficiency of CdS/CdTe solar cells. CdS/CdTe cells were fabricated on numerous float-line-manufacturable TCO and TCO/HRT-coated substrates. The behavior of the best-performing buffer layer was examined over a range of CdS thickness, and the device performance data show gradual dependence of open-circuit voltage and fill factor on CdS thickness below a critical value. The effect of fractional pinhole area is modeled, and it is proposed that pinholes do not dominate device behavior with thinner CdS, and instead band alignment effects explain the observed phenomena. Modeling indicates that the ohmic behavior of the buffer has a relatively small effect on devices with pinholes; instead, improving the diode quality of areas with thin or no CdS has a dominant effect.