Study of power integrity challenges in high-speed I/O design using power rails merging scheme

Modern electronic devices such as tablets and smartphones are getting more powerful and efficient. The demand in feature sets, functionality and usability increase exponentially and this has posed a greater challenge to the design of a power distribution network (PDN). Power rails merging is a popular option adopted today in a PDN design as the provision of numerous power rails is no longer feasible due to form factor limitation and cost constraint. In this paper, a study of power integrity challenges in a high-speed input/output design using power rails merging scheme is presented. Despite having all the advantages such as pin count reduction, decoupling capacitors sharing, lower impedance and cost saving, power rails merging can however, introduce coupling noise to the system. In view of this, a PDN design with power rails merging that fulfills design recommendations and specifications such as noise target, power well placement, voltage supply values as well as power supply quadrant assignment is extremely important.