Title :
Power distribution network modeling using block-based approach
Author_Institution :
Intel Archit. Group (IAG) Intel Microelectonics (M) Sdn. Bhd, Halaman Kampung Jawa, Malaysia
Abstract :
A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be regenerated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be re-extracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.
Keywords :
electronics packaging; microprocessor chips; network routing; printed circuit layout; voltage regulators; S-parameters model; block based PDN modeling; block based approach; board layout; decoupling capacitor; ground terminal; microprocessor chip; package layout; package substrate; power distribution network modeling; power integrity analysis; power rails routing; power terminal; printed circuit board; voltage regulator module; voltage source supply; Capacitors; Integrated circuit modeling; Layout; Power systems; Rails; Routing; Scattering parameters; block-based modeling; impedance profile; power distribution network modeling; power integrity;
Conference_Titel :
Electronics Packaging Technology Conference (EPTC 2013), 2013 IEEE 15th
Conference_Location :
Singapore
Print_ISBN :
978-1-4799-2832-3
DOI :
10.1109/EPTC.2013.6745718