• DocumentCode
    684308
  • Title

    FPGA targeted implementation of a neurofuzzy system for real time TCP/IP traffic classification

  • Author

    Cinti, Alessandro ; Rizzi, Antonello

  • Author_Institution
    Dept. of Inf. Eng., Electron. & Telecommun., Univ. of Rome La Sapienza, Rome, Italy
  • fYear
    2013
  • fDate
    19-21 Oct. 2013
  • Firstpage
    312
  • Lastpage
    317
  • Abstract
    As Internet traffic grows rapidly, it is necessary to monitor and control TCP/IP flows in order to ensure the quality of service and to filter out unwanted traffic by automatic, effective and inexpensive technical solutions. To this aim, especially when dealing with Gbit/s links, real time TCP/IP traffic classification can be performed by dedicated high speed processing devices, avoiding computationally expensive deep packet inspection techniques and relying only on packet features independent of payload content. In this paper we propose to employ an FPGA to design a stand-alone device using only information available at network layer, namely packet sizes, directions and inter-arrival times, to perform flow classification according to application layer protocol (such as HTTP, FTP, SSH, POP3, etc.). The classification system is based on neurofuzzy Min-Max networks, trained by Adaptive Resolution procedures (ARC and PARC algorithms). In order to deal with very high speed links and a large amount of concurrent traffic flows, we propose a complete FPGA targeted implementation of the whole system. Our design is intended to place on a single FPGA all the needed components, including the neurofuzzy Min-Max classifier. The paper describes in detail some interesting technical solutions aiming at optimizing both FPGA working frequency and circuit complexity.
  • Keywords
    Internet; circuit complexity; field programmable gate arrays; fuzzy neural nets; minimax techniques; pattern classification; quality of service; real-time systems; telecommunication traffic; transport protocols; ARC algorithms; FPGA targeted implementation; FPGA working frequency; Internet traffic; PARC algorithm; TCP/IP flow; adaptive resolution procedures; application layer protocol; circuit complexity; classification system; concurrent traffic flow; dedicated high speed processing device; flow classification; high speed links; inter-arrival times; network layer; neurofuzzy min-max networks; neurofuzzy system; packet features; packet sizes; payload content; quality of service; real time TCP/IP traffic classification; stand-alone device; unwanted traffic; Classification algorithms; Engines; Field programmable gate arrays; IP networks; Ports (Computers); Quality of service; Target recognition;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Computational Intelligence (ICACI), 2013 Sixth International Conference on
  • Conference_Location
    Hangzhou
  • Print_ISBN
    978-1-4673-6341-9
  • Type

    conf

  • DOI
    10.1109/ICACI.2013.6748522
  • Filename
    6748522