Optimized pipelining design of transform and quantization for H.264/AVC encoders

In this paper, an optimized pipelining design to deal with the transform and inverse transform together with quantization and rescaling in H.264 video encoders is proposed. By applying the homology of the transform and inverse transform in H.264 and rearranging the sequences of transform and inverse transform of nearby blocks, reconfigurable and low hardware-complexity architectures with a transpose memory can be used to obtain a full-pipelining operation. The proposed architecture was implemented with both a SMIC 0.13 um technology and a Xilinx Virtex6 FPGA. The results show that it can achieve 263M samples/s at 250MHz for transform, quantization and their inverse, which can provide an efficient hardware solution for the H264/AVC encoders.