FPGA based architectural implementation of Context-based Adaptive Variable Length Coding (CAVLC) for H.264/AVC

The latest video compression standard H.264 has adopted Context-based Adaptive Variable Length Coding (CAVLC) as one of its entropy encoding techniques. In this paper, VLSI architecture for implementing CAVLC is proposed. The proposed architecture takes into consideration the bit-rate requirements of H.264 and aims at gaining a high operating clock frequency without involving excessive area. The CAVLC encoder works at a maximum clock frequency of 106 MHz when implemented in Xilinx 10.1i, Virtex-5 technology. The speed is quite appreciable when compared to other existing works. The latency is also reduced. The implemented architecture can achieve the real-time processing requirement for HD-1080 format video sequence.