DocumentCode :
685144
Title :
Mathematical programming models for scheduling in a CPU/FPGA architecture with communication delay
Author :
El Cadi, Abdessamad Ait ; Ben Atitallah, Rabie ; Artiba, Abdelhakim
Author_Institution :
LAMIH, UVHC, Valenciennes, France
fYear :
2013
fDate :
28-30 Oct. 2013
Firstpage :
1
Lastpage :
6
Abstract :
This paper deals with the mathematical modelling of a scheduling problem in a heterogeneous CPU/FPGA architecture with communication delay in order to minimize the makespan, Cmax. This study was motivated by the quality of the available solvers for Mixed Integer Program. The proposed model includes the communication delay constraints in a general form in a heterogeneous case depending at the same time on tasks and computing units. These constraints are linearized without adding any extra variables and the obtained linear model is reduced to make its solving with Cplex 12.5x faster. Computational results show that the proposed model is promising. For an average sized problem up to 50 tasks and 5 computing units the solving time under Cplex is about few seconds.
Keywords :
field programmable gate arrays; integer programming; minimisation; processor scheduling; Cplex; communication delay constraints; computing units; heterogeneous CPU/FPGA architecture; linear model; makespan minimization; mathematical programming modelling; mixed integer program; scheduling problem; Central Processing Unit; Computational modeling; Computer architecture; Data models; Field programmable gate arrays; Mathematical model; Scheduling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Industrial Engineering and Systems Management (IESM), Proceedings of 2013 International Conference on
Conference_Location :
Rabat
Type :
conf
Filename :
6761386
Link To Document :
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