A novel embedded design using High Performance and Low Leakage 6T SRAM Cell based on word decoding scheme at 90 nm technology

Data retention and leakage are among the major areas of concern in contemporary CMOS technology. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines. The paper deals with the designing and analysis of 6T Static Random Access Memory (SRAM) cell focusing primarily over Leakage and delay. The results obtained depict the improvement in the Read Access Time Operation, Write Access Time Operation, Leakage and Stability of a single bit SRAM cell.