ASIC implementation of pipelined ALU

This paper presents a design of 4-bit pipeline arithmetic logic unit (ALU). The novelty of the pipelined ALU is it gives high performance through the pipelining concept compare to non-pipeline ALU. Pipelining is a technique where multiple instruction executions are overlapped. The pipeline modules are independent of each other. All the modules in the ALU design are realized using verilog HDL. Design functionalities are validated through simulation and compilation. Test vectors are created to verify the outputs as opposed to the calculated results. Design simulation is done with ModelSim simulator and RTL synthesis is done with RTL Compiler tool. Physical design of this architecture is done with encounter cadence tool in 180nm technology.