Low power VLSI compressors

We present a new design for a 1-bit full adder featuring hybrid-CMOS design style. Our approach achieves low-energy operations in 180nm technology. The proposed new SERF- full adder (FA) circuit optimized for ultra low power operation is based on modified XNOR gates with clock gating to minimize the power consumption. And also generates full-swing outputs simultaneously. During our simulations, we arrived at the conclusion that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The new adder displayed better power and delay metrics as compared to the standard full adders. To evaluate the performance of the new full adder in a real circuit, we realized 4-2,5-2,5-3,7-2,11-2,15-4,31-5 compressors which are basically used in multiplier modules of DSP filters. Compressor using blockwise power shut down technique is implemented. Simulated results using 180nm CMOS technology are provided. The 32×32 bit MAC unit using proposed full adder without block wise shut down technique produced a power saving of 24.27% over 32 bit MAC designed using SERF full adder and 35.07% power savings over 32 bit MAC designed using conventional 28T full adder.