A high-speed front-end circuit for high-resolution pipelined ADC´s with a merged sample-and-hold amplifier

In this paper, a high-speed front-end circuit for high-resolution pipelined analog-to-digital converters (ADCs) with a merged sample-and-hold amplifier (SHA) is presented. Matching of comparator sampling network and MDAC (multiplying digital-to-analog converter) sampling network, structure of the MDAC, distribution of the time for the three operation phases, and the structure of the reference buffer are discussed. By using the universal structure presented, the speed of the front end circuit is promoted, the power consumption is saved and the reference buffer is simplified. The presented structure of the front-end circuit can be widely used in the pipelined ADCs, especially in the high-speed high-resolution pipeline ADCs.