A 16-channel FPGA-based time-to-digital converter for pulse width modulation circuitry for silicon photomultiplier readout

This work presents a 16-channel time-to-digital converter (TDC) implemented in a field programmable gate array (FPGA) that can be used for a positron emission tomography (PET) detector with pulse width modulation (PWM) circuit readout. Simple tapped delay line methods using dedicated carry chain structures are used to measure short time intervals in conventional TDCs. We propose a TDC with more sophisticated algorithms implemented in a Spartan-6 FPGA, that consists of a fine time measurement block, a coarse counter, a ring oscillator and a buffer. The ring oscillator generates frequency signal related delay chain in order to compensate the process, voltage, and temperature effect in real-time without causing dead-time in the TDC. The performance of our proposed TDC was measured with two input pulses that were generated from a pulse generator. The average timing resolution of the TDC channel is 75.5 ± 13.6 ps FWHM for all 16 channels. The proposed TDC was also used to acquire the flood histogram of the PET detector with a 2 × 2 array of 5 mm × 5 mm position sensitive solid state photo multiplier (PS-SSPM) coupled to an 18 × 18 array of 0.5 mm × 0.5 mm × 1.0 mm LYSO scintillation crystal at room temperature. The proposed TDC with PWM readout circuit clearly identified 0.5 mm × 0.5 mm crystals. In selected rows of crystals, the average ratio of distance between crystal peaks to peak standard deviation was 4.7 and the minimum ratio was 3.2. These results verify the feasibility of our TDC for PET detectors with sub-millimeter width crystals.