An improved method of FPGA-based TDC for time-of-flight PET

Time-to-digital converter (TDC) implemented in field-programmable-gate arrays (FPGAs) with the use of tapped delay line (TDL) methods using dedicated carry chain structures has been utilized to obtain precise timing information for time-of-flight (TOF) PET. However, such chain-structural FPGA-based TDCs suffer from the uneven tap delay, which is one of the main limitations for enhancing the timing performance of TDC. To subdivide the non-uniform tap delay, we propose a TDC with dual-TDL having different starting points. In a FPGA (Spartan-6 LX45, Xilinx USA), two delay lines for a channel were implemented close to the FPGA input pad and one of two delay lines had starting point in further slice from the input pad. In calibration process, the size of wide time bins from the uneven tap delay was reduced using different characteristics of two delay lines. In simulation study, the average time bin size was reduced from 24.7 ps to 12.6 ps and the size of widest time bin was reduced from 168 ps to 56 ps. The performance of the proposed TDC was measured with two input pulses that were generated from a pulse generator. The timing resolution of the TDC was 35 ps FWHM which was improved compared to single-TDL TDC pair (56 ps FWHM). The results of this preliminary study present dual-TDL calibration can effectively improve the time resolution of TDC. The subject of further study will be to extend the number of TDC channels in a FPGA for TOF-PET applications.