Data processing logic for stacked wafer-scale CMOS radiation sensor network

This paper presents a data processing and control logic design for a new radiation detection sensor system that can process data at or above peta-bits-per-second level. We propose a novel data compression method and operation strategy for a radiation sensor array including low power and network-on-wafer solutions. The design goal is to achieve a subtle data compression before the information is ferried to the network, minimizing the loss of information. The result is a radiation detection system that can operate at scan-rate of billion frames per second. The implementation result of the data processing system shows that the intended clock rate is achieved within the power target of less than 200mW.