Dual Stage Time-over-Threshold processing chain for silicon detectors with large capacitance

This paper presents the architecture, simulation and measurement results of a low power dual stage charge sensitive amplifier providing a time-over-threshold analog to digital conversion with linear transfer characteristic dedicated for readout of long silicon strip detectors. The key features of the presented solution are: very low power consumption (2 mW), linear transfer characteristic and low charge losses at high detector capacitance. This work was motivated by the requirements of a new Silicon Tracking System at the Compressed Baryonic Matter experiment at FAIR centre. The issues investigated using other prototype ASICs implementing a constant-current discharge feedback and working with high detector capacitances (tens of pF) directed us to develop the presented idea and to evaluate it with a prototype ASIC. Up to our knowledge, due to the difficult operating conditions this solution fills the gap within the existing fabricated circuits.