Title :
uCache: A Utility-Aware Multilevel SSD Cache Management Policy
Author :
Dejun Jiang ; Yukun Che ; Jin Xiong ; Xiaosong Ma
Author_Institution :
State Key Lab. of Comput. Archit., Inst. of Comput. Technol., Beijing, China
Abstract :
SSD is widely adopted as a cache device thanks to its fast data access and large capacity. In order to complement DRAM-based cache, SSD can serve as a second level cache to form a multilevel cache together with DRAM. However, the inherent features of SSD, such as limited lifetime and slow small writes, make it non-trivial to design a multilevel SSD cache management policy. Traditional DRAM-based cache policies mainly target single level cache, while current SSD cache policies mainly focus on increasing SSD lifetime. In this paper, we propose a utility-aware multilevel SSD cache policy uCache. At the DRAM level, uCache employs a filter to figure out suitable data for SSD caching, and meanwhile uses a buffer to aggregate small writes into large writes. As suitable data blocks are filtered out to enter to SSD, at the SSD level, uCache simply uses LRU to manage cached content. The experimental evaluation shows that uCache can effectively reduce unnecessary writes and avoid slow small writes. Compared to LIRS and Sieve Store, uCache achieves higher utility of SSD in a two-level cache.
Keywords :
cache storage; DRAM-based cache policies; LIRS; LRU; Sieve Store; Solid State Drive; buffer; data blocks; second level cache; uCache; utility-aware multilevel SSD cache management policy; Aggregates; Buffer storage; Hard disks; Hardware; Random access memory; Servers; Throughput; Cache; Lifetime; Performance; SSD; Utility;
Conference_Titel :
High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing (HPCC_EUC), 2013 IEEE 10th International Conference on
Conference_Location :
Zhangjiajie
DOI :
10.1109/HPCC.and.EUC.2013.63