Title :
An IP Protection Algorithm by Watermarking Multiple Scan Chains Based on Minimum Correlation Degree of Vectors
Author :
Wei Liang ; Da-Fang Zhang ; Jing Long ; Yanbiao Li ; Yan-Ji Hu ; Xiong Li
Author_Institution :
Sch. of Inf. Sci. & Eng., Hunan Univ., Changsha, China
Abstract :
With the rapid development of deep sub-micron integrated circuit systems, existing Intellectual Property (IP) watermarking methods for scan chains are mainly implemented by reordering and reconstructing scan chain for protecting reused IP cores. These methods may cause high vector correlation of IP watermark, which will seriously affect overhead and reliability. A multiple scan chains-based IP protection method with minimum test vectors was proposed in this paper. Firstly, the test vector sequence for scan input was generated by the generator of pseudo-random test vector, then the multiple scan chains-based watermarking structure with minimum correlation degree of vectors were constructed by combining the generated sequence with the circuit-under-test. By adding constraints in the structure, watermark would be restricted to positions of certain scan cells. Finally, the watermark was inserted and extracted by altering states of specific registers in scan cells with the designed logic circuit for bit alteration. With no influence on normal circuit function, the proposed algorithm could embed and extract the information of the user´s legitimate ownership and effectively address high power overhead and low security. The experiments were conducted on ISCAS-89 benchmarks. The results showed that the resource overhead in watermark embedding was reduced by more than 8% under the condition of adding constraints.
Keywords :
industrial property; integrated circuit design; logic circuits; logic design; system-on-chip; vectors; IP watermark; ISCAS-89 benchmarks; bit alteration; circuit-under-test; deep submicron integrated circuit systems; high vector correlation; information extract; integrated circuit design; intellectual property watermarking methods; legitimate ownership; logic circuit; minimum correlation degree-of-vectors; multiple scan chain watermarking; normal circuit function; pseudo-random test vector generator; reused IP core protection algorithm; scan chain reconstruction; scan chain reordering; system-on-chip; Algorithm design and analysis; Correlation; IP networks; Logic circuits; Registers; Vectors; Watermarking; IP reuse; minimum correlation degree of vectors; multiple scan chains-based IP watermark; vector correlation;
Conference_Titel :
High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing (HPCC_EUC), 2013 IEEE 10th International Conference on
Conference_Location :
Zhangjiajie
DOI :
10.1109/HPCC.and.EUC.2013.82