Title :
Low Execution Efficiency: When General Multi-core Processor Meets Wireless Communication Protocol
Author :
Fenglong Song ; Yasong Zheng ; Futao Miao ; Xiaochun Ye ; Hao Zhang ; Dongrui Fan ; Zhiyong Liu
Author_Institution :
State Key Lab. of Comput. Archit., Inst. of Comput. Technol., Beijing, China
Abstract :
Inefficient resource utilization of communication cell and base station is the major limitation of traditional Radio Access Network (RAN), which makes Cloud Radio Access Network (C-RAN) becomes a promising infrastructure. C-RAN data centers face physical constraints in space and power, so the efficient utilization of hardware is more critical. General multi-core processors are universally used in modern data centers, and it has become a critical factor of power, computational density and per-operation energy for modern data centers. In this paper, we select User Plane protocol from WCDMA wireless communication protocols, and implement it as a benchmark firstly. The User Plane protocol is responsible for processing and transferring high volume streaming data between user´s mobile terminals and core network. Then, based on its hardware performance counters, we study performance of general multi-core processor when processing User Plane protocol. The evaluation results show that micro-architecture of dominant general multi-core processor is inefficient for User Plane protocol, that is, the dominant micro-architecture mismatches to needs of wireless communication protocols. The random memory access in a large memory address space is a typical characteristic in wireless communication applications, and it incurs high miss ratio of on-chip cache hierarchies. The frequent on-chip cache misses lead to amount of off-chip memory access operations, which incurs longer memory access latency as a dominant factor to degrade overall performance. Finally, we identify the processor´s key micro-architecture characteristics that meet needs of wireless communication protocols, which would lead to improved power efficiency in C-RAN data centers.
Keywords :
cache storage; cloud computing; code division multiple access; multiprocessing systems; protocols; radio access networks; storage allocation; C-RAN data center; WCDMA wireless communication protocol; cloud radio access network; hardware performance counter; low execution efficiency; memory access latency; memory address space; multicore processor microarchitecture; off-chip memory access operation; on-chip cache hierarchy miss ratio; power efficiency; processing User Plane protocol; random memory access; user core network; user mobile terminal; volume streaming data; Base stations; Hardware; Instruction sets; Multicore processing; Protocols; Wireless communication; Data Centers; General Processor Limitation; User Plane Protocol; Wireless Communication Protocol;
Conference_Titel :
High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing (HPCC_EUC), 2013 IEEE 10th International Conference on
Conference_Location :
Zhangjiajie
DOI :
10.1109/HPCC.and.EUC.2013.129