An Anti-power Attacks Implementation of AES Algorithm in ASIC

In this paper, we apply a protective strategy to the AES encryption algorithm. In order to reduce power consumption and correlation in the process of arithmetic operations, we change the trigger number and location in the hardware implementation by modifying the structure of the algorithm. Through the simulation platform, our Advanced Encryption Standard algorithm can effectively resist the Differential Power Analysis and Correlation power analysis. Compared with the mask and dynamic differential logic, the policy doesn´t increase the complexity of the algorithm and the area.