A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI

In this paper, we propose a low-power area-efficient redundant flip-flop for soft errors, called DICE-ACFF. Its structure is based on the reliable DICE (Dual Interlocked storage CEll) and the low-power ACFF (Adaptive-Coupling Flip-Flop). It achieves lower power at lower data-activity. We designed DICE-FF and DICE-ACFF using 65 nm conventional bulk and thin-BOX FD-SOI (Silicon on Thin-BOX, SOTB) processes. Its area is twice as large as the conventional DFF. As for power dissipation, DICE ACFF achieves lower power than the conventional DFF below 20% data activity. When data activity is 0%, its power is half of the DFF. As for soft error rates DICE ACFFs are 1.5x better than conventional DICE FFs based on circuit-level simulations to estimate critical charge. No SEU is observed on the DICE ACFF by α-particle and neutron irradiations on the bulk and SOTB chips. From neutron irradiation results, the soft error rate of the DFF of the SOTB chip is 1/15 compared with that of the bulk chip.