• DocumentCode
    689061
  • Title

    A timing jitter insensitive logic gate using tunable gain dynamics in an SOA and optical thresholding

  • Author

    Yue Tian ; Fok, Mable P. ; Prucnal, Paul R.

  • Author_Institution
    Dept. of Electr. Eng., Princeton Univ., Princeton, NJ, USA
  • fYear
    2013
  • fDate
    9-14 June 2013
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    We experimentally demonstrate a reconfigurable and timing-jitter insensitive AND/NOT gate based on tunable gain dynamics in a semiconductor optical amplifier and optical thresholding. The measured jitter tolerance is up to ±50 ps or ±25 ps for the AND/NOT gate.
  • Keywords
    optical logic; semiconductor optical amplifiers; timing jitter; SOA; jitter tolerance; optical thresholding; reconfigurable AND-NOT logic gate; semiconductor optical amplifier; timing-jitter insensitive AND-NOT logic gate; tunable gain dynamics; Logic gates; Optical fibers; Optical pulses; Optical pumping; Optical signal processing; Semiconductor optical amplifiers; Timing jitter;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Lasers and Electro-Optics (CLEO), 2013 Conference on
  • Conference_Location
    San Jose, CA
  • Type

    conf

  • Filename
    6833442
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=689061