Study of the AES Realization Method on the Reconfigurable Hardware

In order to improve the realization efficiency of AES encryption algorithm based on FPGA and reduce hardware resource utilization. We give a reconfigurable implementation of AES encryption and decryption circuit which supports three different key lengths of AES, AES-128, AES-192, AES-256. It effectively uses the public modules and greatly reduces the chip´s area compared with a single implementation of these modules respectively. Based on reconfigurable ideas, this design uses a state machine to control encryption round number according to the different key lengths, while under module implementation mixed with the inverse of resource sharing, as well as three AES algorithm key expansion shared. The circuit implemented on Xilinx Virtex-V FPGA series, hardware resource consumption is for the 4308 slice. Our experiments show that the maximum operating frequency of 132.5 MHz, 128/192/256-bit AES key length encryption throughput rates of up to 1005/960/740 Mb/s. High throughput ratio/hardware resources can meet the current requirements of most of the wireless sensor network data exchange rate.