Performance evaluation of full adders in ASIC using logical effort calculation

Device scaling has been a relatively straight forward issue in terms of power, speed and noise aspect. For submicron CMOS technology area, topology selection, power dissipation and speed are imperative aspect especially for designing Clocked Storage Element (CSE), adder circuits and MAC unit for high-speed and low-energy design like portable batteries and microprocessors. This paper presents a logical based delay model for different adder topologies in order to obtain minimum delay, minimum number of stages in minimizing the transistor count and the power consumption of the circuit. In this work a full adder is designed with 10 carry and 6 sum logic constructions and its delay is observed with wide spectrum of electrical effort and its performance is observed in terms of number of stages and transistor sizes. From this mathematical analysis the optimized circuits are implemented using Tanner EDA with TSMC MOSIS 250 nm technology and its performance is analyzed in terms of transistor count, delay and power dissipation with respect to the mathematical model. All the logical construction (carry logic and sum logic) used for designing full adder are realized in terms of CMOS logic.