Title :
Interconnect crosstalk noise estimation for high speed integrated circuits
Author :
Kalpana, A.B. ; Hunagund, P.V.
Author_Institution :
Dept. of Electron. & Commun., Bangalore Inst. of Technol., Bangalore, India
Abstract :
This paper presents an accurate Crosstalk noise model for the noise constrained VLSI Interconnect optimization.Compared to earlier crosstalk models, our 8-π model considers the key parameters such as coarse distribution RC characteristics for the victim net and coupling locations, it is very much essential to estimate crosstalk noise peak and noise width to optimize noise aware layout in deep sub-micron technologies.
Keywords :
VLSI; circuit optimisation; crosstalk; integrated circuit interconnections; integrated circuit layout; integrated circuit noise; 8-π model; RC characteristics; VLSI interconnect optimization; coarse distribution; coupling locations; crosstalk noise; deep sub-micron technology; high speed integrated circuits; interconnect crosstalk; noise aware layout; noise constrained; noise estimation; victim net; Crosstalk; Distributed; Interconnect; Model; Noise;
Conference_Titel :
Research & Technology in the Coming Decades (CRT 2013), National Conference on Challenges in
Conference_Location :
Ujire
Electronic_ISBN :
978-1-84919-868-4
DOI :
10.1049/cp.2013.2495
