Time multiplexed online checking — A simple approach

There is a growing demand for online hardware checking capability to cope with increasing in-field failures. There are many online checking schemes available. However, their area overhead remains too high for cost-sensitive applications. In this paper, a Time-Multiplexed Online Checking (TMOC) scheme, using embedded field-programmable blocks for checker implementation, is used for error detection. By using a decoder design, with integer lifting wavelet transform compression technique, and applied filters for compressing the image a significant reduction in chip area for online checkers is achieved. TMOC have been successfully implemented, error detection is displayed in Xilinx flat form window and demonstrated TMOC scheme using a Field-Programmable Gate Array (FPGA) sparten 3E kit.