High-speed radix-4 Add-Compare-Select unit for next generation communication systems

Author

Wooseok Byun ; Ji-hoon Kim

Author_Institution

Dept. of EE, Chungnam Nat. Univ., Daejeon, South Korea

fYear

2013

fDate

17-19 Nov. 2013

Firstpage

1

Lastpage

2

Abstract

ACS (Add-Compare-Select) units are the most important block in FEC (Forward Error Correction) decoders such as Viterbi decoder and Turbo decoder. Due to the increase of performance requirement in next generation mobile communication systems such as LTE-Advanced, high speed operation of ACS units also becomes more important to achieve high throughput requirement. In this paper, we present three types of high-speed radix-4 ACS unit implementation for 12-bit operands and compare hardware complexities for various operating clock periods with 40% margin in 65nm CMOS process.

Keywords

CMOS analogue integrated circuits; Long Term Evolution; Viterbi decoding; forward error correction; mobile communication; turbo codes; FEC decoders; LTE-advanced; Turbo decoder; Viterbi decoder; forward error correction decoders; hardware complexity; high-speed radix-4 ACS unit implementation; high-speed radix-4 add-compare-select unit; next generation communication systems; next generation mobile communication systems; size 65 nm; word length 12 bit; Clocks; Complexity theory; Decoding; Delays; Forward error correction; Hardware; Logic gates; VLSI; add-compare-select; high-speed; retiming;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2013 International

Conference_Location

Busan

Type

conf

DOI

10.1109/ISOCC.2013.6863958

Filename

6863958