• DocumentCode
    692515
  • Title

    A hardware/software cosimulator for Network-on-Chip

  • Author

    Kurimoto, Yosuke ; Fukutsuka, Yusuke ; Taniguchi, Ittetsu ; Tomiyama, Hiroyuki

  • Author_Institution
    Grad. Sch. of Sci. & Eng., Ritsumeikan Univ., Kusatsu, Japan
  • fYear
    2013
  • fDate
    17-19 Nov. 2013
  • Firstpage
    172
  • Lastpage
    175
  • Abstract
    Network-on-Chip (NoC) is considered as a promising interconnection scheme for many-core System-on-a-Chip (SoC) since it offers better scalability than traditional bus-based interconnection. In this paper, we proposed a fast simulator of NoC architectures using QEMU and Noxim. QEMU is an open-source CPU emulator, and Noxim is an open-source SystemC base NoC simulator for on-chip interconnection network. Experimental results show that proposed simulator successfully simulates a 108 core NoC in a practical time.
  • Keywords
    circuit simulation; integrated circuit interconnections; network-on-chip; NoC architecture; Noxim; QEMU; SoC; bus-based interconnection; hardware-software cosimulator; interconnection scheme; many-core system-on-a-chip; network-on-chip; on-chip interconnection network; open-source CPU emulator; open-source SystemC-base NoC simulator; Central Processing Unit; Computational modeling; Computers; Multiprocessor interconnection; Software; System-on-chip; SystemC; instruction-set simulation; network-on-chip; software development support;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2013 International
  • Conference_Location
    Busan
  • Type

    conf

  • DOI
    10.1109/ISOCC.2013.6863964
  • Filename
    6863964