Comparative analysis of 1:1:2 and 1:2:2 FinFET SRAM bit-cell using assist circuit

Read and write yields of 6σ are achieved in 1:1:2 and 1:2:2 FinFET SRAM bit-cells using a negative bit-line write assist circuit and a suppressed word-line read assist circuit, respectively. These two bit-cells are compared in terms of read delay and leakage current. In spite of a smaller cell current, 1:1:2 bit-cell achieves 27.7% smaller read delay than 1:2:2 bit-cell due to a smaller bit-line capacitance. 1:1:2 bit-cell has a smaller leakage current due to the smaller fin number of pass gate transistors, but the difference is just 0.5% because of a larger V_th variation.