DocumentCode :
692538
Title :
Sensing circuit optimization using different type of transistors for deep submicron STT-RAM
Author :
Byungkyu Song ; Taehui Na ; Jisu Kim ; Kang, S.H. ; Jung Pill Kim ; Seong-Ook Jung
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
fYear :
2013
fDate :
17-19 Nov. 2013
Abstract :
In this paper, we propose an optimal combination of transistor types in the conventional sensing circuit. A sensing margin, which determines the read yield of STT-RAM, is sensitive to the Vth type of several transistors in the sensing circuit. Thus, the optimization of the sensing circuit using different types of transistors is important for designing the sensing circuit in STT-RAM. Using industry compatible 45-nm model parameters, Monte Carlo HSPICE simulation results show that the conventional sensing circuit optimized using different types of transistors achieves read access pass yield enhancement of 10% when compared to the conventional sensing circuit using typical transistors.
Keywords :
Monte Carlo methods; circuit optimisation; random-access storage; Monte Carlo HSPICE simulation; STT-RAM read yield; deep submicron STT-RAM; industry compatible model parameter; optimal combination; read access pass yield enhancement; sensing circuit optimization; sensing margin design; size 45 nm; transistor type; Clamps; MOS devices; Nonvolatile memory; Random access memory; Sensors; Torque; Transistors; I-V Curve Analysis; STT-RAM; Sensing Margin; Sensing circuit optimization; read yield;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2013 International
Conference_Location :
Busan
Type :
conf
DOI :
10.1109/ISOCC.2013.6863987
Filename :
6863987
Link To Document :
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