Title :
A spur free 0.4-V 88-μW 200-MHz phase-locked loop
Author :
Joung-Wook Moon ; Kwang-Chun Choi ; Min-Hyeong Kim ; Woo-Young Choi
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm2 and consumes 88 μW at 0.4-V supply for 200-MHz operation.
Keywords :
CMOS integrated circuits; charge pump circuits; phase locked loops; voltage-controlled oscillators; CMOS technology; frequency 200 mHz; low voltage charge pump circuit; power 88 muW; size 130 nm; supply regulated active loop filter; suppressed reference spurs; ultralow voltage phase locked loop; voltage 0.4 V; voltage controlled oscillator; CMOS integrated circuits; CMOS technology; Charge pumps; Leakage currents; Phase locked loops; Voltage measurement; Voltage-controlled oscillators; low voltage charge pump; phase locked loop; power efficiency; spur reduction; ultra low voltage;
Conference_Titel :
SoC Design Conference (ISOCC), 2013 International
Conference_Location :
Busan
DOI :
10.1109/ISOCC.2013.6864005
