Title :
Memory design considerations for high-performance networking SoCs
Author :
Arsovski, I. ; Qing Li ; Kuemerle, Mark ; Rui Tu ; Pilo, H.
Author_Institution :
IBM Syst. & Technol. Group, Essex Junction, VT, USA
Abstract :
On chip memory in today´s networking SoCs takes up >50% of total area and consumes >40% of total power. As demand for high-performance networks grows, so will the memory content on future SoCs. This paper presents IBM´s 32nm HKMG SOI embedded memory offering discussing the considerations associated with the design of key networking memory functions. With memory limiting system performance and dictating minimum voltage system-level power and performance optimization are also presented.
Keywords :
SRAM chips; embedded systems; system-on-chip; embedded memory; high performance networking SoC; memory design; on chip memory; size 32 nm; Arrays; Memory management; Optimization; Ports (Computers); Random access memory; Registers; System-on-chip; dense; embedded DRAM; embedded SRAM; high performance SoC; memory offering;
Conference_Titel :
SoC Design Conference (ISOCC), 2013 International
Conference_Location :
Busan
DOI :
10.1109/ISOCC.2013.6864029
