Title :
Design of delay-locked loop for wide frequency locking range
Author :
Hsun-Hsiang Chen ; Zih-Hsiang Wong ; Shen-Li Chen
Author_Institution :
Dept. of Electron. Eng., Nat. Changhua Univ. of Educ., Changhua, Taiwan
Abstract :
In order to increase the frequency locking range, a delay-locked loop (DLL) circuit with frequency to voltage converter (FVC) and phase select circuit is described. For the low power dissipation consideration, the circuit´s bias current is keep at lower level. The simulation results show that the operating frequency range extend from 106 MHz ~ 151 MHz to 54 MHz ~ 250 MHz, and the power dissipation increases from 2.47 mW ~ 3.33 mW to 6.7 mW ~ 14 mW.
Keywords :
delay lock loops; low-power electronics; voltage-frequency convertors; DLL circuit; FVC; circuit bias current; delay locked loop circuit; frequency 54 MHz to 250 MHz; frequency to voltage converter; low power dissipation; phase select circuit; power 2.47 mW to 3.33 mW; power 6.7 mW to 14 mW; wide frequency locking range; Clocks; Delays; Detectors; Frequency conversion; Generators; Jitter; Voltage control; DLL; FVC;
Conference_Titel :
SoC Design Conference (ISOCC), 2013 International
Conference_Location :
Busan
DOI :
10.1109/ISOCC.2013.6864033
