An equivalence checking algorithm based on cutset match of gate-level circuits

In design process of digital circuits, an equivalence checking algorithm is proposed on cut-set match of a gate-level circuit in order to improve the correctness of the circuit design and time and space efficiency of verification. Firstly of all, the specification and implementation circuits are divided into several set-cuts, which are called logic cones in accordance with partition rules. Secondly, cut-sets of two circuits are matched using matching techniques. Thirdly, an “exclusive-or” gate is connected to outputs of the two matched cut-sets, then the miter circuit is constructed, and the structure is changed to the corresponding conjunctive normal formula. Finally, the miter circuit is proven to be functionally equivalent or not by using the engine of SAT. Experimental results show the feasibility of the approach on the ISCAS´85 benchmark circuits.