Low Power 7-T SRAM Using 90 NM Technology with Tanner Tool

The increasing market of portable electronics devices and battery powered portable electronic systems is making a pressure to the whole chip design industry to reduce the power dissipation of the electronics circuits so that battery backup can be increased. CMOS SRAM memory consumes almost 55% power of the total digital circuit. It is also said that memories are the power hungry devices in any digital system but today no digital system can be completed without memories. This article is based on the motivation of reduction of the dynamic power in SRAM memory and focuses on the analysis in terms of power dissipation, delay and area of the 7-transistor SRAM memory cell at 90 nm technologies by using the Tanner tool. The article targets towards short circuit power dissipation as well as switching power dissipation. The circuit is characterized by using the 90 nm technology which is having a supply voltage of 1.0 volts and threshold voltage is 0.3 volts.