The Design and Implementation of Sigma Delta ADC Digital Decimation Filter

This paper presents a novel implementation of Sigma Delta digital decimation filter with low power and hardware efficient but high performance. The digital decimation filter consists of a modified Cascaded integrator comb decimation filter, one stage compensate filter and one stage half-band filter. The multi-stage signal processing, polyphase technology and CSD code are used to design the filter. We use Simulink and modelsim 6.5 to do the designe and simulation of the decimation filter. The realization of the decimation filter´s hardware is obtained by FPGA Xilinx. Compared to the traditional digital decimation filter, the proposed method has reduced 44% power and saved 65% hardware.