IR to routing challenge and solution for interposer-based design

A novel IR-aware chip and interposer co-design methodology is presented to handle both chip-interposer routing and micro-bump planning for IR drops. Based on bump rules and power information in a chip, the methodology analyzes the locations of micro bumps to meet IR constraints. For chip-interposer routing, the computational geometry techniques (e.g., Delaunay triangulation and Voronoi diagram) are applied to a network-flow formulation for minimizing both IR drops and total wirelength. With the chip and interposer co-design flow, IR constraints can be met with 100% chip-interposer routing completion. Experimental results based on industry designs demonstrate the high-quality of our algorithm.