• DocumentCode
    695311
  • Title

    Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits

  • Author

    Yen-Lung Chen ; Wei Wu ; Liu, Chien-Nan Jimmy ; Lei He

  • Author_Institution
    Electr. Eng. Dept., Nat. Central Univ., Chungli, Taiwan
  • fYear
    2015
  • fDate
    19-22 Jan. 2015
  • Firstpage
    556
  • Lastpage
    561
  • Abstract
    In advanced technology node, not only process variations but also aging effects have critical impacts on circuit performance. Most of existing works consider process variations and aging effects separately while building the corresponding behavior models. Because of the time-varied circuit property, parametric yield need to be reanalyzed in each aging time step. This results in expensive simulation cost for reliability analysis due to the huge number of circuit simulation runs. In this paper, an incremental Latin hypercube sampling (LHS) approach is proposed to build the stochastic behavior models for analog/mixed-signal (AMS) circuits while simultaneously considering process variations and aging effects. By reusing previous sampling information, only a few new samples are incrementally updated to build an accurate stochastic model in different time steps, which significantly reduces the number of simulations for aging analysis. Experiments on an operational amplifier and a DAC circuit achieve 242x speedup over traditional reliability analysis method with similar accuracies.
  • Keywords
    analogue integrated circuits; hypercube networks; integrated circuit reliability; mixed analogue-digital integrated circuits; operational amplifiers; stochastic processes; DAC circuit; Latin hypercube sampling; aging analysis; aging effects; analog circuits; analog/mixed-signal circuits; circuit simulation; lifetime stochastic behavioral modeling; operational amplifier; parametric yield; process variations; reliability analysis; time-varied circuit property; Accuracy; Aging; Analytical models; Hypercubes; Integrated circuit modeling; Stochastic processes; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific
  • Conference_Location
    Chiba
  • Print_ISBN
    978-1-4799-7790-1
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2015.7059065
  • Filename
    7059065