DocumentCode :
695324
Title :
GPU-accelerated parallel Monte Carlo analysis of analog circuits by hierarchical graph-based solver
Author :
Yan Zhu ; Tan, Sheldon X.-D
Author_Institution :
Dept. of Electr. Eng., Univ. of California, Riverside, Riverside, CA, USA
fYear :
2015
fDate :
19-22 Jan. 2015
Firstpage :
719
Lastpage :
724
Abstract :
In this article, we propose a new parallel matrix solver, which is very amenable for Graphic Process Unit (GPU) based fine-grain massively-threaded parallel computing. The new method is based on the graph-based symbolic analysis technique to generate the computing sequence of determinants in terms of determinant decision diagrams (DDDs). DDD represents very simple data dependence and data parallelism, which can be explored much easier by GPU massively-threaded parallel computing than existing LU-based methods. The new method is based on the hierarchical determinant decision diagrams (HDDDs). Inspired by the inherent data parallelism and simple data dependence in the evaluation process of HDDD, we design GPU-amenable continuous data structures to enable fast memory access and evaluation of massive parallel threads. In addition to parallelism in DDD graph, the new algorithm can naturally explore data independence existing in Monte Carlo and frequency domain analysis. The resulting algorithm is a general-purpose matrix solver suitable for fine-grain massive GPU-based computing for any circuit matrices. Experimental results show that the new evaluation algorithm can achieve about two orders of magnitude speedup over the serial CPU based evaluation and more than 4× speedup over numerical SPICE-based simulation method on some large analog circuits.
Keywords :
Monte Carlo methods; analogue integrated circuits; data structures; decision diagrams; frequency-domain analysis; graph theory; graphics processing units; GPU-accelerated parallel Monte Carlo analysis; HDDD; analog circuits; continuous data structures; fine-grain massively-threaded parallel computing; frequency domain analysis; graphic process unit; hierarchical determinant decision diagrams; hierarchical graph-based solver; inherent data parallelism; massive parallel threads; memory access; numerical SPICE; parallel matrix solver; simple data dependence; Algorithm design and analysis; Analog circuits; Graphics processing units; Indexes; Monte Carlo methods; Parallel processing; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
978-1-4799-7790-1
Type :
conf
DOI :
10.1109/ASPDAC.2015.7059095
Filename :
7059095
Link To Document :
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