Systolizing the adaptive decision feedback equalizer using a symbolic state space formulation

A systolic array architecture for the adaptive decision feedback equalizer (ADFE) is proposed in this paper which is based on an algebra developed earlier by Kung et al [5]. Two basic processing cells that are computationally equivalent and easy to realize are used to construct the main body of the array. To satisfy all the desirable features of a systolic array, the array needs to be operated at a clock speed twice that of input. The increase in clock speed can, however, be exploited to reduce the total number of adders and multipliers by about 50%.