Characterization of Interconnect Process Variation in CMOS Using Electrical Measurements and Field Solver

An electrical methodology to extract the complete set of interconnect process parameters is developed. A new structure comprising a combination of integrated meander resistor and a comb-capacitor sandwiched between bottom and top plates is proposed. Its electrical characterization provides all the necessary measurement data required for reliable and robust extraction of interconnect parameters, namely, interconnect thickness, width, as well as dielectric thickness and dielectric constant. A nonlinear optimizer based on the simulated annealing method coupled with an accurate random walk field solver is used for this purpose. The measurements are performed on a 130-nm Cu CMOS process and the extracted parameters are shown to be within 6% of the values obtained from cross-sectional scanning electron microscope (XSEM) data. Further, the applicability of the methodology to characterize the interconnects in more advanced technology nodes is also discussed.