Experiments on designing low power decimation filter for multistandard receiver on heterogeneous targets

This work presents the results of different experiments conducted on a power-efficient decimation filter design in a wireless multi-standard receiver context. This paper evaluates the efficiency of some low-power solutions applied to the digital filtering domain. This evaluation was done for heterogeneous target devices and for both ASIC and FPGA technologies. With this work, the authors prove that identifying the best low-power solution is very dependent on technology and target device.