DocumentCode :
698385
Title :
C-based rapid prototyping for digital signal processing
Author :
Casseau, Emmanuel ; Le Gal, Bertrand ; Bomel, Pierre ; Jego, Christophe ; Huet, Sylvain ; Martin, Eric
Author_Institution :
LESTER Lab., UBS Univ., France
fYear :
2005
fDate :
4-8 Sept. 2005
Firstpage :
1
Lastpage :
4
Abstract :
The increasingly demanding requirements of digital signal processing applications like multimedia, new generations of wireless systems, etc. led to the definition of more and more complex algorithms and systems that are to be efficiently implemented with the time to market constraint. Today, the electronic system design community is mainly concerned with defining efficient System-on-a-Chip (SoC) design methodologies in order to benefit from the high integration capabilities of current ASIC and FPGA technologies on the one hand, and manage the increasing algorithmic complexity of applications on the other hand. Rapid prototyping is considered as a key to speed up the system design. In this context, we have introduced a novel methodology that efficiently addresses both the algorithmic complexity and the high flexibility required by the various application profiles. Our methodology benefits from the emerging High-Level Synthesis (HLS) tools in a platform-based approach dedicated to the rapid prototyping of real-time systems. We show the effectiveness of this approach with the design of a DVB-DSNG compliant receiver.
Keywords :
digital video broadcasting; direct broadcasting by satellite; field programmable gate arrays; high level synthesis; logic design; radio receivers; signal processing; system-on-chip; time to market; ASIC technology; C-based rapid prototyping; DVB-DSNG compliant receiver; FPGA technology; HLS tools; SoC design methodologies; algorithmic complexity; digital satellite news gathering; digital signal processing; digital video broadcasting; electronic system design community; high-level synthesis; multimedia; system-on-a-chip; time to market constraint; wireless systems; Algorithm design and analysis; Computer architecture; Decoding; Digital video broadcasting; Hardware; Throughput; Viterbi algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Conference, 2005 13th European
Conference_Location :
Antalya
Print_ISBN :
978-160-4238-21-1
Type :
conf
Filename :
7077970
Link To Document :
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