An energy-efficient reconfigurable FFT/IFFT processor based on a multi-processor ring

Author

Guichang Zhong ; Fan Xu ; Willson, Alan N.

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA

fYear

2004

fDate

6-10 Sept. 2004

Firstpage

2023

Lastpage

2026

Abstract

We have designed and built a single-chip reconfigurable FFT/IFFT processor that employs a ring-structured multiprocessor architecture. Multi-level reconfigurability is realized by dynamically allocating computation resources required by specific applications. The processor IC has been fabricated in TSMC 0.25-μm CMOS. It performs 8-point to 4096-point FFT/IFFT with power-scalable features and provides useful trade-offs between algorithm flexibility, implementation complexity and energy efficiency.

Keywords

CMOS integrated circuits; energy conservation; fast Fourier transforms; low-power electronics; microprocessor chips; reconfigurable architectures; TSMC CMOS; energy-efficient reconfigurable FFT/IFFT processor; fast Fourier transform; multiprocessor ring; power-scalable features; ring-structured multiprocessor architecture; single-chip reconfigurable FFT/IFFT processor; size 0.25 mum; Abstracts; CMOS integrated circuits; Hardware design languages; Program processors; Prototypes; Reconfigurable architectures; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Conference, 2004 12th European

Conference_Location

Vienna

Print_ISBN

978-320-0001-65-7

Type

conf

Filename

7079792