DocumentCode :
699470
Title :
Architecture design for FPGA implementation of finite interval CMA
Author :
Hermanek, Antonin ; Schier, Jan ; Regalia, Phillip
Author_Institution :
Dept. Commun., Images & Inf. Process., Inst. Nat. des Telecommun., Evry, France
fYear :
2004
fDate :
6-10 Sept. 2004
Firstpage :
2039
Lastpage :
2042
Abstract :
In the paper, we present the architecture design of the Finite Interval Constant Modulus Algorithm (FI-CMA) for FPGA implementation. For floating point calculations required in the algorithm we use the library based on the Logarithmic Number System (LNS). In the design, the resource reuse and minimization of the total latency is emphasized.
Keywords :
field programmable gate arrays; floating point arithmetic; signal processing; FPGA implementation; LNS; advanced DSP algorithm; architecture design; finite interval CMA; finite interval constant modulus algorithm; floating point calculations; library based logarithmic number system; resource reuse; total latency minimization; Abstracts; Computer architecture; Computers; Digital signal processing; Field programmable gate arrays; Random access memory; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Conference, 2004 12th European
Conference_Location :
Vienna
Print_ISBN :
978-320-0001-65-7
Type :
conf
Filename :
7080000
Link To Document :
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