Implementation of two-dimensional discrete cosine transform and its inverse

In this paper, the implementation of a unified 8 × 8 discrete cosine transform (DCT) and its inverse is described. First, the accuracy of the structure that has been reported earlier is analyzed with Matlab in order to have internal word length requirements for the implementation. Then, the structure is modeled as a data path structure with Synopsys Module Compiler. When synthesizing the model with 19-bit internal word length onto 0.11 μm CMOS technology, the resulting pipeline exhibits an operation frequency of 253 MHz and uses 40 000 equivalent gates. The latency for both transforms is 94 cycles. Finally, the comparison to another unified pipeline structure reveals up to 15% smaller estimated area.