• DocumentCode
    700036
  • Title

    Orthogonal correction implementation for time interleaved analog-to-digital converters: Realtime application

  • Author

    Ferre, G. ; Le Gal, B. ; Bossuet, L. ; Jridi, M. ; Dallet, D. ; Colucci, P.

  • Author_Institution
    IMS Lab., Univ. of Bordeaux 1, Talence, France
  • fYear
    2008
  • fDate
    25-29 Aug. 2008
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    To significantly increase the sampling rate of an ADC, time-interleaved ADC (TIADC) is an efficient solution. Due to the manufacturing process, the main drawback of a TIADC system is that the M ADCs, which compose this end, are not exactly the same. This means that offset, gain and time mismatch errors are introduced. These errors cause distortions in the output sampled signal and introduce unwanted tones and noise, and hence, reduce the spurious free dynamic range (SFDR) as well as the signal to noise ratio (SNR). In this paper, we propose a new orthogonal digital calibration implementation, for timing skew, offset and gain mismatches, based on Code Division Multiple Access (CDMA) technique. Our calibration is online, this means that errors can be estimated while the ADC is running. Since most of the calibration processes are carried out on the digital outputs, very little change is needed on the analog part of the ADC. Simulation and implementation results show respectively the efficiency of our proposed calibration algorithm and our hardware implementation.
  • Keywords
    analogue-digital conversion; code division multiple access; signal denoising; signal sampling; ADC sampling rate; CDMA technique; SFDR reduction; SNR reduction; TIADC system; code division multiple access technique; gain error; offset error; orthogonal correction implementation; orthogonal digital calibration implementation; signal distortion; signal to noise ratio reduction; spurious free dynamic range reduction; time interleaved analog-to-digital converter; time mismatch error; unwanted noise; unwanted tones; Abstracts; Field programmable gate arrays; Hardware; Registers; Simulation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Conference, 2008 16th European
  • Conference_Location
    Lausanne
  • ISSN
    2219-5491
  • Type

    conf

  • Filename
    7080568