A flexible architecture for DSP applications combining high performance arithmetic with small scale configurability

This paper presents the architecture of a flexible and high performance unit for DSP applications. The proposed architecture operates based on fast Carry-Save (CS) arithmetic. A mapping methodology, for datapaths composed with the proposed flexible units, is also presented. It exploits the incorporated features of the proposed units and enables fast computations, high operation densities and advanced data reusability. Experimental results shown that several DSP algorithms can be mapped onto the proposed architecture with high efficiency delivering in average, latency gains of 36.56% and 45.76% compared to the MAC and the primitive resources based datapaths, respectively.