A robust histogram-based image segmentation ASIC design for System-on-Chip using 65nm technology

Author

Salahat, Ehab ; Saleh, Hani ; Zitouni, M. Sami ; Sluzek, Andrzej S. ; Mohammad, Baker ; Al-Qutayri, Mahmoud ; Ismail, Mohammad

fYear

2015

fDate

17-19 Feb. 2015

Firstpage

1

Lastpage

4

Abstract

Image segmentation is an essential preprocessing step for many computer vision and image processing applications. Implementing algorithms that handle such images in hardware will speed up the processing task considerably. In this paper, a new robust histogram-based image segmentation ASIC design of a System-on-Chip (SoC) using 65nm technology is presented. With a clock frequency of 289 MHz, the SoC can reach a frame rate of a 4410 FPS for an image resolution of 256×256. This is few order of magnitudes faster than the FPGA implementation in the literature. The finished-chip details renders it suitable for real-time and mobile applications.

Keywords

application specific integrated circuits; computer vision; image resolution; image segmentation; real-time systems; system-on-chip; FPGA implementation; SoC; System-on-Chip; clock frequency; computer vision; image processing; image resolution; image segmentation ASIC design; mobile applications; real-time applications; robust histogram; Field programmable gate arrays; Histograms; Image resolution; Image segmentation; Random access memory; System-on-chip; ASIC; Histogram-Based Thresholding; Image Processing; Image Segmentation; Real-Time; System-on-Chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Signal Processing, and their Applications (ICCSPA), 2015 International Conference on

Conference_Location

Sharjah

Type

conf

DOI

10.1109/ICCSPA.2015.7081298

Filename

7081298